Unijunction Transistor

INTRODUCTION:-
The basic structure of a unijunction transistor (UJT) is shown in Fig.1. It is essentially a bar of N type semiconductor material into which P type material has been diffused somewhere along its length. Contacts are then made to the device as shown; these are referred to as the emitter, base 1 and base 2 respectively. Fig.2 shows the schematic symbol used to denote a UJT in circuit diagrams. For ease of manufacture alternative methods of making contact with the bar have been developed, giving rise to the two types of structure - bar and cube.

DIAGRAMS..

The equivalent circuit shown in Fig.4 has been developed to explain how the device works, and it is necessary to define the terms used in this explanation.

R_BB is known as the interbase resistance, and is the sum of R_B1 and R_B2:

R_BB = R_B1 + R_B2

N.B. This is only true when the emitter is open circuit.

V_RB1 is the voltage developed across R_B1; this is given by the voltage divider rule:

         RB1
VRB1 =         
      RB1 + RB2  

Since the denominator of equation 2 is equal to equation 1, the former can be rewritten as:

       RB1 
VRB1 =    x VBB 
       RBB

The ratio R_B1 / R_BB is referred to as the intrinsic standoff ratio and is denoted by (the Greek letter eta).

If an external voltage V_e is connected to the emitter, the equivalent circuit can be redrawn as shown in Fig..

If Ve is less than V_RB1, the diode is reverse biased and the circuit behaves as though the emitter was open circuit. If however V_e is increased so that it exceeds V_RB1 by at least 0.7V, the diode becomes forward biased and emitter current Ie flows into the base 1 region. Because of this, the value of R_B1 decreases. It has been suggested that this is due to the presence of additional charge carriers (holes) in the bar. Further increase in V_e causes the emitter current to increase which in turn reduces R_B1 and this causes a further increase in current. This runaway effect is termed regeneration. The value of emitter voltage at which this occurs is known as the peak voltage V_P and is given by: V_P = _AVV_BB + V_D

The characteristics of the UJT are illustrated by the graph of emitter voltage against emitter current.

As the emitter voltage is increased, the current is very small - just a few microamps. When the peak point is reached, the current rises rapidly, until at the valley point the device runs into saturation. At this point R_B1 is at its lowest value, which is known as the saturation resistance.

The simplest application of a UJT is as a relaxation oscillator, which is defined as one in which a capacitor is charged gradually and then discharged rapidly. The basic circuit is shown in Fig.7; in the practical circuit of Fig.8 R3 limits the emitter current and provides a voltage pulse, while R2 provides a measure of temperature compensation. Fig. 9 shows the waveforms occurring at the emitter and base 1; the first is an approximation to a sawtooth and the second is a pulse of short duration.

The operation of the circuit is as follows: C1 charges through R1 until the voltage across it reaches the peak point. The emitter current then rises rapidly, discharging C1 through the base 1 region and R3. The sudden rise of current through R3 produces the voltage pulse. When the current falls to I_V the UJT switches off and the cycle is repeated.

It can be shown that the time t between successive pulses is given by:

           VBB - VV
t + R1C ln         secs (5) Megaohms. C in µF. 
           VBB - VP

The oscillator uses a 2N2646 UJT, which is the most readily available device, and is to operate from a 10V D.C. power supply.

From the relevant data sheet the specifications for the 2N2646 are:

VEB2O IE(peak) PTOT(max) IP(max) IV(max)            Case style TO18
 30V  2A       300mw     5µA    4ma    0.56 - 0.75 

It is important that the value of R1 is small enough to allow the emitter current to reach I_P when the capacitor voltage reaches V_P and large enough so that the emitter current is less than I_V when the capacitor discharges to V_V. The limiting values for R1 are given by:

          VBB - VP               VBB - VV
R1(max) =         and R2(min) =         
             IP                    IV

From the specifications for the 2N2646 the average value of is 0.56 + 0.75/2 = 0.655. Substituting this value in equation (4) and assuming V_D = 0/7V: V_P = 0.655 x 10 + 0.7 = 7.25V.

So R1(max) = 10 - 7.25/5µA = 550K, and if VV = approx VBB/10, 
   R1(min) = 10 - 1/4mA = 2.25K.

If we choose a value for R1 somewhere between these limits, e.g. lOK, the value of C can be calculated from equation.

If f = 1MHz, t = 1/f = 1msec. V_BB - V_P = 10 - 7.25 = 2.75 and V_BB - V_V = 10 - 1 = 9

                                                          t 
                                                                
Rearranging equation(5) to make C the subject: C =        VBB - VV
                                                   R1 ln          
                                                          VBB - VP

           0.001
so C =                = approx 84nF. 
       104 ln (9/2.75)

Because of component and UJT tolerances it is sufficient in most circumstances to use an approximate formula: f = 1/CR, which assumes that is 0.63 - well within 5% of the average value for the 2N2646. In practice one would use a variable resistance (or a variable resistance in series with a fixed resistance) for R1 so that the frequency of oscillation could be adjusted to give the required value.

R2 is not essential; if it is included, a value of 470 ohms is appropriate for the 2N2646. The value of R3 should be small in comparison with R_BB, with which it is in series, so as to prevent it from affecting the value of the peak voltage. A value of 47 ohms or thereabouts is satisfactory.

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COMMON EMITTER CONFIUGRATION

INTRODUCTION..

The COMMON-EMITTER CONFIGURATION (CE) is the most frequently used configuration in practical amplifier circuits, since it provides good voltage, current, and power gain. The input to the CE is applied to the base-emitter circuit and the output is taken from the collector-emitter circuit, making the emitter the element "common" to both input and output. The CE is set apart from the other configurations,
because it is the only configuration that provides a phase reversal between input and output signals.


CIRCUIT DIAGRAM..


PURPOSE....

The COMMON-BASE CONFIGURATION (CB) is mainly used for impedance matching, since it has a low input resistance and a high output resistance. It also has a current gain of less than 1. In the CB, the input is applied to the emitter, the output is taken from the collector, and the base is the element common to both input and output

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Norton's Theorem

Norton's Theorem

In some ways Norton's Theorem can be thought of as the opposite to "Thevenins Theorem", in that Thevenin reduces his circuit down to a single resistance in series with a single voltage. Norton on the other hand reduces his circuit down to a single resistance in parallel with a constant current source. Norton's Theorem states that "Any linear circuit containing several energy sources and resistances can be replaced by a single Constant Current generator in parallel with a Single Resistor". As far as the load resistance, R_L is concerned this single resistance, R_S is the value of the resistance looking back into the network with all the current sources open circuited and I_S is the short circuit current at the output terminals as shown below.

Norton's equivalent circuit.

The value of this "Constant Current" is one which would flow if the two output terminals where shorted together while the source resistance would be measured looking back into the terminals, (the same as Thevenin).

For example, consider our now familiar circuit from the previous section.

To find the Nortons equivalent of the above circuit we firstly have to remove the centre 40Ω load resistor and short out the terminals A and B to give us the following circuit.

When the terminals A and B are shorted together the two resistors are connected in parallel across their two respective voltage sources and the currents flowing through each resistor as well as the total short circuit current can now be calculated as:

with A-B Shorted Out

If we short-out the two voltage sources and open circuit terminals A and B, the two resistors are now effectively connected together in parallel. The value of the internal resistor Rs is found by calculating the total resistance at the terminals A and B giving us the following circuit.

Find the Equivalent Resistance (Rs)

Having found both the short circuit current, Is and equivalent internal resistance, Rs this then gives us the following Nortons equivalent circuit.

Nortons equivalent circuit.

Ok, so far so good, but we now have to solve with the original 40Ω load resistor connected across terminals A and B as shown below.

Again, the two resistors are connected in parallel across the terminals A and B which gives us a total resistance of:

The voltage across the terminals A and B with the load resistor connected is given as:

Then the current flowing in the 40Ω load resistor can be found as:

which again, is the same value of 0.286 amps, we found using Kirchoff's circuit law in the previous tutorials.

Nortons Analysis Summary.

The basic procedure for solving Nortons Analysis equations is as follows:

• 1. Remove the load resistor R_L or component concerned.
• 2. Find R_S by shorting all voltage sources or by open circuiting all the current sources.
• 3. Find I_S by placing a shorting link on the output terminals A and B.
• 4. Find the current flowing through the load resistor R_L.

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Thevenins Theorem

Thevenins Theorem states that "Any linear circuit containing several voltages and resistances can be replaced by just a Single Voltage in series with a Single Resistor". In other words, it is possible to simplify any "Linear" circuit, no matter how complex, to an equivalent circuit with just a single voltage source in series with a resistance connected to a load as shown below. Thevenins Theorem is especially useful in analyzing power or battery systems and other interconnected circuits where it will have an effect on the adjoining part of the circuit.

Thevenins equivalent circuit.

As far as the load resistor R_L is concerned, any "One-port" network consisting of resistive circuit elements and energy sources can be replaced by one single equivalent resistance Rs and voltage Vs, where Rs is the source resistance value looking back into the circuit and Vs the open circuit voltage at the terminals.

For example, consider the circuit from the previous section.

Firstly, we have to remove the centre 40Ω resistor and short out (not physically as this would be dangerous) all the emf´s connected to the circuit, or open circuit any current sources. The value of resistor Rs is found by calculating the total resistance at the terminals A and B with all the emf´s removed, and the value of the voltage required Vs is the total voltage across terminals A and B with an open circuit and no load resistor Rs connected. Then, we get the following circuit.

Find the Equivalent Resistance (Rs)

Find the Equivalent Voltage (Vs)

We now need to reconnect the two voltages back into the circuit, and as V_S = V_AB the current flowing around the loop is calculated as:

so the voltage drop across the 20Ω resistor can be calculated as:

V_AB = 20 - (20Ω x 0.33amps) = 13.33 volts.

Then the Thevenins Equivalent circuit is shown below with the 40Ω resistor connected.

and from this the current flowing in the circuit is given as:

which again, is the same value of 0.286 amps, we found using Kirchoff´s circuit law in the previous tutorial.

Thevenins theorem can be used as a circuit analysis method and is particularly useful if the load is to take a series of different values. It is not as powerful as Mesh or Nodal analysis in larger networks because the use of Mesh or Nodal analysis is usually necessary in any Thevenin exercise, so it might as well be used from the start. However, Thevenins equivalent circuits of Transistors, Voltage Sources such as batteries etc, are very useful in circuit design.

Summary.

The basic procedure for solving Thevenins Analysis equations is as follows:

• 1. Remove the load resistor R_L or component concerned.
• 2. Find R_S by shorting all voltage sources or by open circuiting all the current sources.
• 3. Find V_S by the usual circuit analysis methods.
• 4. Find the current flowing through the load resistor R_L.

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SR Flip Flop

An SR Flip-Flop can be considered as a basic one-bit memory device that has two inputs, one which will "SET" the device and another which will "RESET" the device back to its original state and an output Q that will be either at a logic level "1" or logic "0" depending upon this Set/Reset condition. A basic NAND Gate SR flip flop circuit provides feedback from its outputs to its inputs and is commonly used in memory circuits to store data bits. The term "Flip-flop" relates to the actual operation of the device, as it can be "Flipped" into one logic state or "Flopped" back into another.

The simplest way to make any basic one-bit Set/Reset SR flip-flop is to connect together a pair of cross-coupled 2-input NAND Gates to form a Set-Reset Bistable or a SR NAND Gate Latch, so that there is feedback from each output to one of the other NAND Gate inputs. This device consists of two inputs, one called the Reset, R and the other called the Set, S with two corresponding outputs Q and its inverse or complement Q.

SR Flip Flop Component Outline

SR Flip Flop Circuit Diagram

"Set" State

Consider the circuit shown above. If the input R is at logic level "0" (R = 0) and input S is at logic level "1" (S = 1), the NAND Gate Y has at least one of its inputs at logic "0" therefore, its output Q must be at a logic level "1" (NAND Gate principles). Output Q is also fed back to input A and so both inputs to the NAND Gate X are at logic level "1", and therefore its output Q must be at logic level "0". Again NAND gate principals. If the Reset input R changes state, and now becomes logic "1" with S remaining HIGH at logic level "1", NAND Gate Y inputs are now R = "1" and B = "0" and since one of its inputs is still at logic level "0" the output at Q remains at logic level "1" and the circuit is said to be "Latched" or "Set" with Q = "1" and Q = "0".

"Reset" State

In this second stable state, Q is at logic level "0", Q = "0" its inverse output Q is at logic level "1", not Q = "1", and is given by R = "1" and S = "0". As gate X has one of its inputs at logic "0" its output Q must equal logic level "1" (again NAND gate principles). Output Q is fed back to input B, so both inputs to NAND gate Y are at logic "1", therefore, Q = "0". If the set input, S now changes state to logic "1" with R remaining at logic "1", output Q still remains LOW at logic level "0" and the circuit's "Reset" state has been latched.

Truth Table for this Set-Reset Function

It can be seen that when both inputs S = "1" and R = "1" the outputs Q and Q can be at either logic level "1" or "0", depending upon the state of inputs S or R BEFORE this input condition existed. However, input state R = "0" and S = "0" is an undesirable or invalid condition and must be avoided because this will give both outputs Q and Q to be at logic level "1" at the same time and we would normally want Q to be the inverse of Q. However, if the two inputs are now switched HIGH again after this condition to logic "1", both the outputs will go LOW resulting in the flip-flop becoming unstable and switch to an unknown data state based upon the unbalance. This unbalance can cause one of the outputs to switch faster than the other resulting in the flip-flop switching to one state or the other which may not be the required state and data corruption will exist. This unstable condition is known as its Meta-stable state.

Then, a bistable latch is activated or Set by a logic "1" applied to its S input and deactivated or Reset by a logic "1" applied to its R. The SR Latch is said to be in an "invalid" condition (Meta-stable) if both the Set and Reset inputs are activated simultaneously.

As well as using NAND Gates, it is also possible to construct simple 1-bit SR Flip-flops using two NOR Gates connected the same configuration. The circuit will work in a similar way to the NAND gate circuit above, except that the invalid condition exists when both its inputs are at logic level "1" and this is shown below.

NOR Gate SR Flip-flop

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Superposition Theorem

Superposition Theorem

Superposition theorem is one of those strokes of genius that takes a complex subject and simplifies it in a way that makes perfect sense.

The strategy used in the Superposition Theorem is to eliminate all but one source of power within a network at a time, using series/parallel analysis to determine voltage drops (and/or currents) within the modified network for each power source separately. Then, once voltage drops and/or currents have been determined for each power source working separately, the values are all “superimposed” on top of each other (added algebraically) to find the actual voltage drops/currents with all sources active.

Let’s look at our example circuit and apply Superposition Theorem to it:

Since we have two sources of power in this circuit, we will have to calculate two sets of values for voltage drops and/or currents, one for the circuit with only the 28 volt battery in effect. . .

. . . and one for the circuit with only the 7 volt battery in effect

When re-drawing the circuit for series/parallel analysis with one source, all other voltage sources are replaced by wires (shorts), and all current sources with open circuits (breaks).

Analyzing the circuit with only the 28 volt battery





Analyzing the circuit with only the 7 volt battery




Super Imposing Voltage

Super Imposing current

Final Circuit


REVIEW
The Superposition Theorem states that a circuit can be analyzed with only one source of power at a time, the corresponding component voltages and currents algebraically added to find out what they’ll do with all power sources in effect.

To negate all but one power source for analysis, replace any source of voltage (batteries) with a wire; replace any current source with an open (break).

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Multiplexer

Introduction

Multiplexers are used in building digital semiconductor such as CPUs and graphics controllers. In these applications, the number of inputs is generally a multiple of 2 (2, 4, 8, 16, etc.), the number of outputs is either 1 or relatively small multiple of 2, and the number of control signals is related to the combined number of inputs and outputs. For example, a 2-input, 1-output mux requires only 1 control signal to select the input, while a 16-input, 4-output mux requires 4 control signals to select the input and 2 to select the output.

Multiplexers are also used in communications; the telephone network is an example of a very large virtual mux built from many smaller discrete ones. Instead of having a direct connection from every telephone to every telephone - which would be physically impossible - the network "muxes" individual telephones onto one of a small number of wires as calls are placed. At the receiving end, a demultiplexer, or "demux", chooses the correct destination from the many possible destinations by applying the same principle in reverse.

There are more complex forms of multiplexers. Time-division multiplexers, for example, have the same input/output characteristics as described above, but instead of having a control signal, they alternate between all possible inputs at precise time intervals. By taking turns in this manner, many inputs can share one output. This technique is commonly used on long distance phone lines, allowing many individual phone calls to be spliced together without affecting the speed or quality of any individual call. Time-division multiplexers are generally built as semiconductor devices, or chips, but can also be built as optical devices for fiber optics applications.

Even more complex are code-division multiplexers. Using mathematical techniques developed during World War II for cryptographic purposes, they have since found application in modern cellular networks. Generally referred to by the acronim "CDMA" - Code Division Multiple Access - these semiconductor devices work by assigning each input a unique complex mathematical code. Each input applies its code to the signal it receives, and all signals are simultaneously sent to the output. At the receiving end, a demux performs the inverse mathematical operation to extract the original signals.

Example

The circuit symbol for the above multiplexer is:

Two input multiplexer

One circuit I've received a number of requests for is the multiplexer circuit. This is a digital circuit with multiple signal inputs, one of which is selected by separate address inputs to be sent to the single output. It's not easy to describe without the logic diagram, but is easy to understand when the diagram is available.

The multiplexer circuit is typically used to combine two or more digital signals onto a single line, by placing them there at different times. Technically, this is known as time-division multiplexing.

Input A is the addressing input, which controls which of the two data inputs, X0 or X1, will be transmitted to the output. If the A input switches back and forth at a frequency more than double the frequency of either digital signal, both signals will be accurately reproduced, and can be separated again by a demultiplexer circuit synchronized to the multiplexer.

This is not as difficult as it may seem at first glance; the telephone network combines multiple audio signals onto a single pair of wires using exactly this technique, and is readily able to separate many telephone conversations so that everyone's voice goes only to the intended recipient. With the growth of the Internet and the World Wide Web, most people have heard about T1 telephone lines. A T1 line can transmit up to 24 individual telephone conversations by multiplexing them in this manner.

A very common application for this type of circuit is found in computers, where dynamic memory uses the same address lines for both row and column addressing. A set of multiplexers is used to first select the row address to the memory, then switch to the column address. This scheme allows large amounts of memory to be incorporated into the computer while limiting the number of copper traces required to connect that memory to the rest of the computer circuitry. In such an application, this circuit is commonly called a data selector.

Multiplexers are not limited to two data inputs. If we use two addressing inputs, we can multiplex up to four data signals. With three addressing inputs, we can multiplex eight signals.

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