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The counter output wanted is set by a jumper. Ten counter outputs are available: 8/16/32/64/128/256/512/1024/4096 and 8192 counts. If the 555 is set to oscillate at exactly 1.0Hz by the on-board trimpot then the maximum timer interval which can be set is 8192 seconds (just over 2 hours.) At the end of the counting of the countdown timer period a pulse is output on the pin with the jumper on it. The 14020 ripple counter advances its count on each negative transistion of the clock pulse from the 555. So for each output cycle of low-high-low-high the count is advanced by two. It can be set to an zero state (all outputs low) by a logic high applied to pin 11.
In this circuit C3, R4 and D1 are arranged as a power-on reset. When power is applied to the circuit C3 is in a discharged state so pin 11 will be pulled high. C3 will quickly charge via R4 and the level at pin 11 falls thus enabling the counter. The 14020 then counts clock pulses until the selected counter output goes high. D1 provides a discharge path for C3 when the power is disconnected.
You can change the components values of R1 and C1 to set the 555 count frequency to more than 1.0 Hz. If you change the count to 10 seconds then a maximum timer delay of 81920 seconds, or 22.7 hours, can be obtained.
Transistors:-
A traditional metal–oxide–semiconductor (MOS) structure is obtained by growing a layer of silicon dioxide (SiO2) on top of a silicon substrate and depositing a layer of metal or polycrystalline silicon (the latter is commonly used). As the silicon dioxide is a dielectric material, its structure is equivalent to a planar capacitor, with one of the electrodes replaced by a semiconductor.
When a voltage is applied across a MOS structure, it modifies the distribution of charges in the semiconductor. If we consider a P-type semiconductor (with NA the density of acceptors, p the density of holes; p = NA in neutral bulk), a positive voltage, VGB, from gate to body (see figure) creates a depletion layer by forcing the positively charged holes away from the gate-insulator/semiconductor interface, leaving exposed a carrier-free region of immobile, negatively charged acceptor ions (see doping (semiconductor)). If VGB is high enough, a high concentration of negative charge carriers forms in an inversion layer located in a thin layer next to the interface between the semiconductor and the insulator. Unlike the MOSFET, where the inversion layer electrons are supplied rapidly from the source/drain electrodes, in the MOS capacitor they are produced much more slowly by thermal generation through carrier generation and recombination centers in the depletion region. Conventionally, the gate voltage at which the volume density of electrons in the inversion layer is the same as the volume density of holes in the body is called the threshold voltage.
This structure with P-type body is the basis of the N-type MOSFET, which requires the addition of an N-type source and drain regions.
The operation of a MOSFET can be separated into three different modes, depending on the voltages at the terminals. In the following discussion, a simplified algebraic model is used that is accurate only for old technology. Modern MOSFET characteristics require computer models that have rather more complex behavior. For example, see Liu and the device modeling list at Designers-guide.org.
For an enhancement-mode, n-channel MOSFET, the three operational modes are:
Cutoff, subthreshold, or weak-inversion mode When VGS <>th: where Vth is the threshold voltage of the device. According to the basic threshold model, the transistor is turned off, and there is no conduction between drain and source. In reality, the Boltzmann distribution of electron energies allows some of the more energetic electrons at the source to enter the channel and flow to the drain, resulting in a subthreshold current that is an exponential function of gate–source voltage. While the current between drain and source should ideally be zero when the transistor is being used as a turned-off switch, there is a weak-inversion current, sometimes called subthreshold leakage.In weak inversion the current varies exponentially with gate-to-source bias VGS as given approximately by:
The JFET gate is sometimes drawn in the middle of the channel (instead of at the drain or source electrode as in these examples). This symmetry suggests that "drain" and "source" are interchangeable, so the symbol should be used only for those JFETs where they are indeed interchangeable (which is not true of all JFETs).
Officially, the style of the symbol should show the component inside a circle (representing the envelope of a discrete device). This is true in both the US and Europe. The symbol is usually drawn without the circle when drawing schematics of integrated circuits. More recently, the symbol is often drawn without its circle even for discrete devices.
Electronics is the study and use of electrical that operate by controlling the flow of electrons or other electrically charged particles in devices such as thermionic valves. and semiconductors. The pure study of such devices is considered as a branch of physics, while the design and construction electronic circuits to solve practical problems is called electronic engineering.